1. Field of the Invention
The present invention relates to nonvolatile semiconductor memory and, particularly, to nonvolatile semiconductor memory having a selector for selecting a memory device and controlling a write current.
2. Description of Related Art
Flash memory, which is one of nonvolatile semiconductor memory, has been widely used recently. Recent electrically data rewritable memory such as flash memory has a large capacity, and a smaller semiconductor device of a memory cell has been developed accordingly. In spite of the recent increase in memory capacity, the number of input/output terminals of a memory product remains the same as before. Therefore, large capacity memory generally has a hierarchical selector for selecting a memory device, thereby achieving efficient use of a memory area with a small number of input/output terminals. A sector, which is a data rewriting unit, includes a plurality of memory devices. Each memory device stores data as a charge injected to the memory device.
An example of conventional memory is described in Japanese Unexamined Patent Application Publication No. H04-74391. FIG. 13 shows a pattern diagram of a plane layout of the memory. The memory includes Y10 selector 13100 to Y1m selector 1310m (which are referred to herein collectively as the Y1 selector 1310) to serve as high order selectors, and Y10DEC 13110 to Y1mDEC 1311m (which are referred to herein collectively as the Y1DEC 1311) for controlling the Y1 selector 1310. Each of the Y1 selector 1310 has n number of cells. The cells have the same structure. For example, the n-th cell 1305n has a Y2n selector 1312n to serve as a low order selector, a decoder Y2nDEC 1313n for controlling the Y2n selector 1312n, a sector 1314n and a decoder XnDEC 1315n for controlling memory devices in the sector. The capacity of the memory depends on the number of the selectors Y1 selector 1310, the decoders Y1DEC 1311 and the cells.
The memory also includes a PAD 1301 for making connection with an external device, an input/output circuit 1302 having an input/output buffer, an input/output controller 1303 for controlling a signal between the input/output circuit 1302 and an internal device, and an internal booster 1304 for generating a boosted voltage used internally. The memory further includes a group of write circuits 1306, which includes WC0 to WC15, for supplying a write voltage to a memory device and a group of sense amplifiers 1307, which includes SA0 to SA15, for reading stored data. Each cell is connected to the write circuit group 1306 and the sense amplifier group 1307 through wiring 1308.
When reading stored data, the sense amplifiers 1307 read the data stored in the memory device. The data is then supplied to the outside through the input/output controller 1303, the input/output circuit 1302, and the PAD 1301.
When writing data into a memory device of 0n, the group of write circuits 1306 supplies a write voltage and write control current to the memory device to which data is to be written according to an input signal input from the outside through the PAD 1301, the input/output circuit 1302 and the input/output controller 1303. Further, the decoder Y10DEC 13110 selects a predetermined Y10 selector 13100 and the decoder Y2nDEC 1313n selects a predetermined selector in the Y2n selector 1312n according to the input signal. Also according to the input signal, the decoder XnDEC 1315n selects a predetermined memory device in the Cn sector 1314n. The write voltage and the write control current from the write circuit group 1306 are supplied to the selected memory device in the Cn sector 1314n through the selected Y10 selector 13100 and Y2n selector 1312n. The memory device accumulates electrons in a storage node of a cell transistor according to the write voltage and the write control current supplied by the above operation, thereby storing data.
FIG. 14 is a circuit diagram of a data memory circuit when storing data into a memory device. The data memory circuit shown in FIG. 14 includes a write circuit WC0, a transistor QY1 which is a selected Y10 selector, a transistor QY2 which is a selected Y2n selector, and a selected memory device QX. The write circuit WC0 has a write gate QW1 and a control transistor QK. The gate terminal of the write gate QW1 is supplied with a voltage VR and the source terminal is supplied with a write control voltage VPDD, and the drain terminal is connected to the drain terminal of the control transistor QK. The gate terminal of the control transistor QK is supplied with a controlled voltage VPGD. The voltage VPGD determines a write control current IL of the control transistor QK. The source terminal of the control transistor QK serves as an output of the write circuit WC0.
The output of the write circuit WC0 and the drain terminal of the transistor QY1 in the next stage are connected by a long wiring length for the sake of layout, and therefore wiring resistance R exist therebetween. Thus, a wiring resistor R is placed in the circuit diagram shown in FIG. 14.
The gate terminal of the transistor QY1 is supplied with a voltage VPPG from Y10DEC 10110. The drain terminal of the transistor QY1 serves as an input terminal of a cell. The source terminal of the transistor QY1 is connected to the drain terminal of the transistor QY2 in the next stage.
The gate terminal of the transistor QY2 is supplied with a voltage VPPG from Y2nDEC 13130. The source terminal of the transistor QY2 is connected to the drain terminal of a memory device QX in the next stage. A voltage between the source terminal of the transistor QY2 and the memory device QX serves as a write voltage VD.
The gate terminal of the memory device QX is supplied with a voltage VPPG from XnDEC 1315n, and the source terminal is supplied with a voltage CS to be a predetermined voltage in each mode of writing, erasing and reading. When writing data, the memory device QX is supplied with a write control current IL from the write circuit WC0 according to the write voltage VD. The current IL causes electrons to be accumulated in a memory node of the memory device QX, thereby storing data.
FIG. 15 shows a relationship between the current IL and the voltage VD. For example, in the layout shown in FIG. 13, when writing data from the write circuit WC15 into a cell mn, the relationship between the write control current IL and the write voltage VD is as indicated by a write current curve a shown by full line in FIG. 15. The voltage at an origin A of the current curve is a value that is a result of subtracting a threshold voltage VT of the control transistor QK and a product of the wiring resistance R and the current IL from the control voltage VPGD. Since a distance between the write circuit WC15 and the cell mn is short, the wiring resistance R is very small. Thus, the voltage at the origin A may be substantially represented by VPGD-VT. When writing data from the write circuit WC15 into a cell 0n, the relationship between the write control current IL and the write voltage VD is as indicated by a write current curve b shown by dotted line in FIG. 15. Since a distance between the write circuit WC15 and the cell 0n is long, the wiring resistance R is large and the slope of the current curve b is smaller than that of the current curve a. An origin B of the write voltage VD is represented by VPGD-VT-R*IL. Thus, the voltage at the origin of the current curve decrease as the distance from the write circuit to the cell increases. For example, if a write circuit and a cell mn are wired with an aluminum line having a resistance of 0.07Ω/□ per unit area at a width of 5 μm and a length of 100 μm, the wiring resistance R is approximately (100 μm/5 μm)*0.07Ω/□=1.4Ω. On the other hand, a write circuit and a cell On are wired at a width of 5 μm and a length of 10,000 μm, the wiring resistance R is approximately (10,000 μm/5 μm)*0.07Ω/□=1.40Ω.
In FIG. 15, the graph shown by dash-dotted line indicates current-voltage characteristics of a memory device QX. When storing data into the memory device QX, the voltage at an intersection in the graph of the write current characteristics and the current-voltage characteristics of the memory device QX needs to be higher than a write lower limit voltage. A write speed is higher if a voltage at the intersection is a higher.
Since a write circuit sets a write voltage for a memory device in conventional memory, an actual write voltage supplied to the memory device has a level that subtracts a voltage drop due to wiring resistance from a level set by the write circuit. The wiring resistance varies depending on a length from a write circuit to a memory device or a location of a memory device on a chip. Thus, the write voltage varies depending on the layout on a chip, and therefore a write speed varies accordingly. If manufacturing variations of devices, such as variations in threshold voltage and shape, occurs write defect, the voltage at the intersection in the graph of the write current characteristics and the current-voltage characteristics of the memory device falls lower than the write lower limit voltage, which can cause write defect.